"The Colecovision is Coleco's third
generation video game console, released in August 1982. It offered
arcade-like graphics and controllers, and an initial catalog of 12
titles, with 10 more promised titles on the way. All told,
approximately 170 titles were released on plug-in cartridges during its
lifetime. The controller was a flat joystick, two side buttons, and a
number-pad, which allowed the user to put inserts for customized
buttons. The majority of titles in its catalog were conversions from
coin-operated arcade games."
Actual photos taken by compiling and running the core here
Content
This project recreates most of the circuits found on the
original console PCB including CPU, RAM, video and sound
generation.
Here is a detailed list of internal components:
- Z80 CPU - T80
core from opencores.org
/ fpgaarcade.com
Copyright (c) 2001-2002 Daniel Wallner (jesus at opencores.org)
Ver 300 started tidyup, MikeJ March 2005
Latest version from www.fpgaarcade.com (original www.opencores.org)
- TMS992xA
Video Display Processor
- SN76489AN
sound generator
- General purpose I/O for controller
- Clock generator - operates with main 10.7 MHz clock (external
or PLL)
- Reset generator - requires power-on reset capability of FPGA
External components are:
- BIOS ROM - 8 kByte
- CPU RAM - 1 kByte
- Video RAM - 16 kByte
- Cartridge ROM - up to 32 kByte
- RGB DACs
- Audio DAC
Download the latest version 2.1 of the FPGA Colecovision project here:
fpga_colecovision_2.1.tar.gz
Note, on Windows machines you may have to save the ZIP file before you
can open it. Make sure the extension is .tar.gz
It contains two fully functional system toplevels for
Simple Solution's Zefant
XS3-1000 on the Mini-ITX board (Xilinx Spartan3 1000) and the
Cyclone Board by
JOP.design (Altera Cyclone
EP1C12).
Resource Usage
Fitting results for the Spartan3 1000 (XC3S1000FG456):
Please note that this design contains additional logic
for the AC97 controller and additional RAM for the scan doubler.
Logic Utilization:
Total Number Slice Registers: 1,055 out
of 15,360 6%
Number used as Flip
Flops:
1,054
Number used as
Latches:
1
Number of 4 input
LUTs: 3,478
out of 15,360 22%
Logic Distribution:
Number of occupied
Slices:
2,149 out of 7,680 27%
Number of Slices containing only related
logic: 2,149 out of 2,149 100%
Number of Slices containing unrelated
logic: 0 out
of 2,149 0%
*See NOTES below for an explanation of
the effects of unrelated logic
Total Number 4 input
LUTs: 3,684 out
of 15,360 23%
Number used as
logic:
3,478
Number used as a
route-thru: 76
Number used for Dual Port RAMs: 128
(Two LUTs used per Dual Port RAM)
Number used as Shift
registers: 2
Number of bonded
IOBs:
255 out of 333 76%
IOB Flip
Flops:
50
Number of Block
RAMs:
15 out of 24 62%
Number of
GCLKs:
3 out of 8 37%
Number of
DCMs:
1 out of 4 25%
Total equivalent gate count for design: 1,030,301
Following is the flow summary for the Altera Cyclone device:
+------------------------------------------------------------------------+
; Flow
Summary
;
+-------------------------+----------------------------------------------+
; Flow
Status
; Successful - Wed Mar 01 22:33:20
2006 ;
; Quartus II Version ; 5.0 Build 168
06/22/2005 SP 1 SJ Web Edition ;
; Revision
Name ;
jop_cv
;
; Top-level Entity Name ;
jop_cv
;
;
Family
;
Cyclone
;
;
Device
;
EP1C12Q240C8
;
; Timing
Models ;
Final
;
; Met timing requirements ;
Yes
;
; Total logic elements ; 3,217 / 12,060 ( 26 %
)
;
; Total
pins
; 139 / 173 ( 80 %
)
;
; Total virtual pins ;
0
;
; Total memory bits ; 204,800 /
239,616 ( 85 %
)
;
; Total
PLLs
; 1 / 2 ( 50 %
)
;
+-------------------------+----------------------------------------------+
Legal Issues
Redistribution and use in source and synthesized forms, with or without
modification, are permitted provided that the following conditions are
met:
Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
Redistributions in synthesized form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
Neither the name of the author nor the names of other contributors may
be used to endorse or promote products derived from this software
without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
See also the file COPYING.
Please note:
The copyright of the ROM images is owned by third parties, thus the
above does not apply to them. You have to be entitled separately to use
the ROM images together with the FPGA Colecovision design. Owning an
original Colecovision console and the cartridges might be ok, but I am
not liable for any
copyright
violations that arise from your use of the FPGA Colecovision design.
I will ignore any requests for a copy of the ROM images.
References
Colecovision:
TMS9928:
SN76489:
--
Arnim Läuger
<arnim.laeuger at gmx.net>
