Calculating PLL params for dedicated SYSCLK/VIDCLK

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For using the video converter block, an exact ratio between SYSCLK and VIDCLK is needed to sync on the very same video frame rate. For this purpose I set up a small program. The base search algorithm (C++) comes from Mike, I ported it to JAVA (including some further range checking/limitations for the allowed PLL output frequencies and incorporating the clock divider of the clock module of the Replay framework) and set up a simple GUI.

Basically it is required to set the desired video output (currently only one is supported) and the system clock and native video size (in H-pixels and V-lines) from the core. It then calculates several possible settings for M,N,P for the PLL on the Replay board. One can then select a line out of the list which fits best – usually nearest to the ideal clock the core should run for best (gaming) experience. It did not do any extra work like sorting the results and removing double entries, I expect this can be much easier done by the user by just looking at it instead of blowing up the application code for such stuff…

It is developed using the latest ADT environment, works on Android (>=2.3.3) or should work on any free/commercial emulator on Win, Mac, Linux (just search the web, there are several ones). I tested it on a “real” Nexus 7 II, a “real” POV Mobii 10.1 with custom ROM (VegaComb) and on the BlueStacks emulator on Win 7. This should allow to use it on most OS w/o significant increase of my development efforts. And I have to say it was surprisingly easy for me to set it up…

Sources and pre-compiled APK file is on SVN under /src/sw/tools/ReplayPllCalc. The application looks like this:

The Mvid/Nvid/Pvid parameters are used for the PLL/clock output on y4 (setting VIDCLK), the Msys/Nsys/Psys parameters correspond to y0 (setting SYSCLK). Maybe I’ll do some more update on this, because SYSCLK can be somewhat misleading. For now I ment the “effective” system clock the target core needs (to generate its video signal, to be precise), practically the SYSCLK is just CLK_A (or y0 at the PLL output) divided by 4 (by a DCM in the clock generator/distribution unit of the Replay framework), which needs to be gated using an additionally generated clock enable signal (for now it can be set to :3 or :4 in my tool).

This is needed as the SYSCLK needs to be faster/as fast as the max. possible SPI clock from the ARM processor to handle this interface. In a future release I may also check that this is fulfilled and having a proposed clock gating ratio as output instead of an user input here…

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