Writing INI files

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This post explains the main functions of the config reader I implemented. It is not yet complete and thus work-in-progress (so there are already more things implemented not described yet). I also kept the descriprions quite brief for now…


The ini setup has to be prepared by the developer of a Replay target core.
– As user, do NOT modify any settings until adviced to do so (e.g. famous “overclocking”)
– Developers should think twice when using e.g. non-standard PLL settings

Especially bad timing setups may cause overheating or bus collisions which could (even slowly) damage board components. Feel free to contact me or Mike if special setups are needed.

Ok, you have been warned, let’s get down to business…


Ini files are read by the Replay loader to set up the board. On power-up, the Replay loader looks for a file called “replay.ini” in the root directory of an inserted SD-card and processes it. It contains further information like what FPGA configuration file should be used and how the hardware has to be initialized. It can be also used to set up a menu system for the user to allow further settings once a design is set up on the FPGA.

Furthermore, the very same format is used to save user settings after modified in the OSD menu.

The INI file is a plain ASCII file and can be edited with any text editor. Please don’t mix it with Windows ini files, although it uses a very similar syntax:

# this is a comment


keyword1 = value1 , value2 , ... 

keyword2 = "text value with blanks", 12345 , text_avoiding_blanks , ...

# another comment

# Supported decimal numbers:
# ----------------------------------
# 12345 decimal value (base 10)
# 0x123 hexadecimal value (base 16)
# 01234 octal value (base 8)
# *0101 binary value (base 2)


Section: [SETUP] (pre-FPGA-configuration)

BIN = fpga_config_file.bin

Points to the FPGA configuration file to load. It must be located in the same directory of the ini file.

INFO = “some information”

Allows to post some user information on the OSD status screen.

CLOCK = <clock_params>

Basic PLL setup. It allows to use pre-defined settings (for standard video modes) or a parameter setup.

<clock_params> can be one of this options:

  • PAL
    113.5MHz  for y0 (SYSCLK)
    17.73MHz  for y1 (Coder)
    49.152MHz for y2 (AUDCLK)
    disabled  y3 (Expansion Main)
    27MHz     for y4 (VIDCLK)
    disabled  y5 (Expansion Small)
  • NTSC
    114.5MHz  for y0 (SYSCLK)
    14.32MHz  for y1 (Coder)
    49.152MHz for y2 (AUDCLK)
    disabled  y3 (Expansion Main)
    27MHz     for y4 (VIDCLK)
    disabled  y5 (Expansion Small)
  • HD74
    114.5MHz  for y0 (SYSCLK)
    disabled  y1 (Coder)
    49.152MHz for y2 (AUDCLK)
    disabled  y3 (Expansion Main)
    74.25MHz  for y4 (VIDCLK)
    disabled  y5 (Expansion Small)
  • M1,N1,M2,N2,M3,N3,ps0,ps1,ps2,ps3,ps4,ps5,pd0,pd1,pd2,pd3,pd4,pd5,ys0,ys1,ys2,ys3,ys4,ys5
    M,N … three PLL are setup by 27MHz * N / M (must be within 80…250MHz)
    ps … selects one of the three PLL as source for the six outputs
    pd … divider factor for each of the six outputs
    ys … enable for each of the six outputs



Enables SVHS/composite video output coder (if fitted on the Replay board and if it
matches to the video mode generated by the loaded core).

<norm> can be one of this options:

  • PAL
  • NTSC

VFILTER=<p1>, <p2>, <p3>

Sets the analogue video filter bandwidth and DC level for all 3 channels.
(Relevant for DVI-A/VGA and Composite/SVHS).


Notifies that the FPGA configuration routes the i2c lines for further
video configuration by the ARM. <twi> has to be 0 or 1.


Notifies that the FPGA configuration uses the spi lines for further
configuration <cfg> and OSD video <osd> by the ARM. <cfg> and <osd> has to be 0 or 1.


Sets the SPI clock speed, be aware that SPI is also used for the SD-card, reducing it
slows file access, too fast may not allow to use the SD-card at all.
Details on <value> will follow…


Configures the behaviour of the button on the replay board.

<mode> can be one of this options:

  • OFF
  • MENU
Section: [SETUP] (post-FPGA-configuration)


Video DAC configuration settings (16 bytes). <twi> must be 1 on EN_TWI to use this keyword.


Initial setup of 32 static and 32 dynamic bits set in the FPGA syscon module. <cfg> must be set to 1
on EN_SPI to use this keyword. It can be changed later in the configurable menu system.

Section: [UPLOAD] (post-FPGA-configuration)


Enables verification feature, reads back and verifies any ROM/DATA upload when <ver> is set to 1. Otherwise
upload is done “blindly”.


Defines a ROM upload. <cfg> must be set to 1 on EN_SPI to use this keyword.

Section: [MENU] (post-FPGA-configuration)


Define a new menu page with a given title.


Define a new menu entry with a given name and bitmask.

OPTION=”string”,<value>, default

Define an additional option for a menu entry which can be selected.

Special menu item: file stream upload

ITEM=”string”, loadselect, <startadr>

Define a new menu entry which allows the user to browse for a file with extension “EXT” and upload
to a given FPGA adress. Optionally, if <verify> is set to 1, it will also perform a second run reading the
FPGA data back and check it against the selected file again. The FPGA must handle the data properly,
so compute them byte by byte on upload and send the exact stream back (when verification is enabled).
The option string must be always “*.” + extension, everything else will not show the menu item.

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