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The active device is an Altera EPM7064STC44-10. It is a high performance 5 Volt programmable device, containing 64 Macrocells (about 1,250 gates) and will run up to 100 MHz.

Data sheet available here

Free design software can be downloaded from their website. Design Tools
( MAX+PLUS II BASELINE Software )

The device is programmed through its JTAG pins, using any of Altera's download cables.
'Byteblaster' is the cheapest and most simple - you can make your own.

Two user IO pins (6 and 10 on the Altera) MUST be driven low, which help reduce ground bounce.

Pins 1 and 2 on the module are wired to 2 Altera pins each. This is because the clock pins are input only.
If you wish to use Pin1 as a input , drive PIN_1_OUT <= 'Z' (tristate). To use as an output just use PIN_1_OUT and the input will be ignored.

Here is an example design you can use as a base for your own, which should make things clearer.
It requires a clock of about 10 MHz on PIN 1, and will flash LEDs which are wired to the remaining IO pins via a current limiting resistor. Test.vhd is the example code, and Test.acf is a compiler generated configuration file that puts the pins in the correct place - The tools will pick it up automatically.

TEST.VHD
TEST.ACF


Contact me if you require any design services.

Pinout table for reference :
Device EPM7064STC44-10
Altera Pin DIL Pin Altera Pin DIL Pin
37 Input (GCK1) 1 18 I/O 15
35 I/O 1 19 I/O 16
40 Input (GCK2) 2 20 I/O 17
42 I/O 2 21 I/O 18
43 I/O 3 22 I/O 19
44 I/O 4 23 I/O 20
2 I/O 5 25 I/O 21
3 I/O 6 28 I/O 22
5 I/O 7 31 I/O 23
8 I/O 8 27 I/O 24
11 I/O 9 30 I/O 25
12 I/O 10 33 I/O 26
13 I/O 11 34 I/O 27
14 I/O 12 9,17,29,41 VCC 28
15 I/O 13
4,16,24,36 GND 14
6 I/O GND IO Pin, must be driven low
10 I/O GND IO Pin, must be driven low
38 Input (OE1) GND
39 Input (GCLR) GND
7 Input TMS
1 Input TDI
26 Input TCK
32 Output TDO

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