<![CDATA[FPGA Arcade — VIC20]]> http://www.fpgaarcade.com/punbb/index.php Sat, 08 Mar 2014 10:03:50 +0000 PunBB <![CDATA[Moderating the VIC-20 topics...]]> http://www.fpgaarcade.com/punbb/viewtopic.php?id=259&action=new To keep sub-topics readable, I started to moderate them. Of course, no post will get lost.

Please feel free to start a new topic if it does not directly fit to the existing ones, to keep readability of the subtopics.

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Sat, 08 Mar 2014 10:03:50 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?id=259&action=new
<![CDATA[Miscellaneous topics, mainly floppy disk support]]> http://www.fpgaarcade.com/punbb/viewtopic.php?id=229&action=new Track lengths vary with G64 files, just as they do with flux.  Flux data provides the exact bitcell time for the data separator.  Instead of shifting in the bits from the G64, you use the bitcell times... It's actually much simpler and automatically handles everything that G64 images don't provide (like multiple densities on a single track). Bitcells are currently fixed at 16 bits, and will probably remain that way.  I made a provision in the format to use any width, but I do not see a case where this will ever be necessary.  The flux data is the very same data that comes off the head.  If you want 100% compatibility, flux is the only way.

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Tue, 04 Feb 2014 17:11:13 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?id=229&action=new
<![CDATA[VIC-20 & 1541 core and downloads]]> http://www.fpgaarcade.com/punbb/viewtopic.php?id=227&action=new Thanks for trying the core (and mentioning that the download was missing - simply missed this, as I said the sources were released long before), I had the impression it was not really of interest for anyone.  big_smile

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Thu, 30 Jan 2014 07:30:01 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?id=227&action=new
<![CDATA[VIC-20 & 1541 core status and compatibility list]]> http://www.fpgaarcade.com/punbb/viewtopic.php?id=226&action=new Please only post compatibility info in this thread.

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Wed, 29 Jan 2014 21:52:32 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?id=226&action=new
<![CDATA[VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?id=165&action=new With a clear head it was easy to see the issue.. the problem was with the replacement for the Xilinx RAM, in Mike's original code there were 8 x RAM16X1D's, but the VHDL for the non Xilinx equivalent was actually an 8x8 array.  Most of the time the RAM is accessed with a 3 bit address, but not always - hence the issue and corruption of RAM contents.  Change the RAM to a 16x8 and all is good !  It was timing dependent as to if RAM address 7 got corrupted, and the corruption was also only for bit 0, hence why 2 (row/col 07) didn't work.  So the MIST VIC20 core is bad, as well as other ports non Xillnx ports of the VIC20!  No issue here for the Replay version because its T65 core is good and the PS2 to VIA interface code is completely different to the MIST.

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Sun, 10 Nov 2013 12:32:17 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?id=165&action=new