<![CDATA[FPGA Arcade — VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?id=165 Fri, 09 Jun 2017 10:38:55 +0000 PunBB <![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10784#p10784 With a clear head it was easy to see the issue.. the problem was with the replacement for the Xilinx RAM, in Mike's original code there were 8 x RAM16X1D's, but the VHDL for the non Xilinx equivalent was actually an 8x8 array.  Most of the time the RAM is accessed with a 3 bit address, but not always - hence the issue and corruption of RAM contents.  Change the RAM to a 16x8 and all is good !  It was timing dependent as to if RAM address 7 got corrupted, and the corruption was also only for bit 0, hence why 2 (row/col 07) didn't work.  So the MIST VIC20 core is bad, as well as other ports non Xillnx ports of the VIC20!  No issue here for the Replay version because its T65 core is good and the PS2 to VIA interface code is completely different to the MIST.

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Fri, 09 Jun 2017 10:38:55 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10784#p10784
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10779#p10779 Mike - Thanks - but I already have a version of VIC20_PS2_IF.vhd that does away with the Xilinx RAM16X1D RAM and from what I can see in simulation today that seems to be behaving correctly, so I'm not sure that it comes down to the RAM.

Today I've been playing with and hacking the kernel keyboard routines and the issue may relate to LSR not correctly setting the carry flag under certain circumstances, but I can't understand (yet) why LSR works correctly for other keys in the matrix that produce the same ROW value..   More debugging and a clear head is required I think!

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Thu, 08 Jun 2017 16:10:12 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10779#p10779
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10776#p10776 Very odd. I can modify the vic RTL to remove the RAM16X1D. If you can simulate it that would be awesome.
I'm a bit sick at the moment, but I'm still trying to fix a board for you. I have the parts now.

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Thu, 08 Jun 2017 11:04:10 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10776#p10776
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10772#p10772 Thanks for the feedback ,but unfortunately its not as simple as the joystick interfering..   On further investigation this is really an issue for the MIST board, however from the T65 bug thread on this forum it seems wolfgang worked with wsoltys on the issue for the MIST board and its only the MIST source that has the modified T65 with the additional SaveP that actually breaks the operation the 6502 !! I don't have a MIST board on which to verify if the 6502 is broken in the same way as my port, but I suspect it is !!

The 2 key issue would appear to be down to timing, if I read the keyboard matrix directly via manipulation the VIA ports the matrix reads just fine.   But if I read the matrix via a bit of assembler that disables the normal interrupt routine and loops calling the kernel keyboard scan function then only very occasionally will I see a "2" key press, its very random, so its a problem with the way the kernel scans the keyboard matrix and a function of the timing of its interaction with the VIA's.

I suspect the issue may come down to the different RAM used in the PS2 to VIA interface code, which is Mike's originally and is used on the MIST board, my port and other ports of the VIC20 core, e.g. ZX-UNO, but NOT on the Replay board.

It's interesting as the ZX-UNO code seemingly has no reported issues and is using unmodified PS2 and T65 sources, the difference could be that the UNO is a Spartan FPGA and the MIST is an Altera Cyclone.   The PS2 interface code uses a Xilinx RAM16X1D primitive for Xilinx FPGA's and plain VHDL for an equivalent (uninferred) Altera RAM - I am thinking something related to this RAM is the root cause and I'm now trying to simulate the whole PS/2 interface to see if I can see where the issue may lie !

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Wed, 07 Jun 2017 13:30:47 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10772#p10772
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10767#p10767 non working keys imply that one of the portbits is being pulled low when it shouldnt. i'd look at the joystick port and everything connected to it. (you can make 2 not work by pulling one of the joystick lines)

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Tue, 06 Jun 2017 15:20:22 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10767#p10767
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10747#p10747 Opening up an old topic here.. why the 2 and " keys don't work on certain ports of the VIC20 core !  I see this issue on my port running on a MAX10 and at some point a fix was suggested by wsoltys in the T65 6502 core which involved setting SaveP <= '1' in T65_MCode.

However it seems this is a bad fix because that breaks the T65 core and causes it to not set the zero flag in certain circumstances (e.g. DEC $900E) .

I'm curious as to how it was determined that setting SaveP was a fix ? My original VIC20 core port ran fine with the 2 key working and it seems to be changes to the VIA code that actually prevent it from working, not the 6502, however the core has moved on and now I've been unable to find a version of the 6522 that gives me a working 2 key so I can't compare to try to determine the issue!

As I'm working in VIA fixes I want to properly understand the issue with the 2 key, especially if it is really a VIA issue !   The only potential issues reported for the T65 for my compile are inferred latches on the Q2_t variable in the ALU, which I'll look at, but any history on the issue is appreciated!

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Fri, 02 Jun 2017 11:53:25 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10747#p10747
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10584#p10584 I thought I had. I'll do so again now!

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Wed, 10 May 2017 10:14:07 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10584#p10584
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10583#p10583 Not sure if you sent me an E-Mail, I've been off on holiday for a couple of weeks and I've only just finished catching up on E-Mail, but I didn't spot anything in my inbox or junk...  I'm still happy to do what I can with regards to fixes smile !!

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Wed, 10 May 2017 08:26:41 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10583#p10583
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10368#p10368 I'll mail him this evening, very happy to get help backporting fixes etc.

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Thu, 13 Apr 2017 12:33:06 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10368#p10368
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10364#p10364 Give the man a board and SVN access! big_smile

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Thu, 13 Apr 2017 11:22:18 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10364#p10364
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10363#p10363 Thanks Mike, yes the MiST core is all based off your original code, and it isn't that different to your source I can see in your public SVN.  I thought I would approach you as the original author rather than the MiST folks, but most fixes are probably applicable to both cores.

Right now I have some VIA fixes that address some of the failures in the viavarious tests that are part of the VICE emulator test suite.  These VICE tests are good because they answer some of the questions in the VHDL as to when timers are reloaded etc.  There are still issues with the VIA VHDL - especially around timer 2 when it changes mode from pulse counting to a one shot countdown timer and vice versa, but I'm still working on those issues.

Is there a good way to get details to you ?  I should be able to indicate which change to the VHDL fixes specific tests in the viavarious test suite, so if you can run a .prg file on your VIC20 core you should be able to easily validate that the issue exists and that it's properly fixed by my changes.

Kevin

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Thu, 13 Apr 2017 09:50:06 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10363#p10363
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10354#p10354 I haven't looked at the MIST code, but it may well be based on mine. Wolfgang re-wrote it for Replay.
I'm certainly open to look at any issues, and I'll check what's released compared with the internal svn.

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Wed, 12 Apr 2017 06:42:14 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10354#p10354
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10351#p10351 Hi - does anyone have any good feeling on the level of compatibility of this core to the original hardware?

I'm not using the FPGA source Arcade source or hardware but I do have a port of the original VIC20 FPGA core on my own Altera MAX10 hardware that is based off the MiST source and I'm finding out that probably around 50% of games have issues.  From what I can gather the MiST source is a branch of the original and the FPGA Arcade versions should really be the 'master' and  therefore best at this time ??

I've fixed quite a few things myself, but I admit I'm struggling to fix some of the more obscure issues.  To try to identify issues I have been running the test programs from the VICE emulator which does highlight obvious differences with the VIA's and VIC chips for one, but I don't know if they are really a problem when it comes to games.  The VIA FPGA implementation for example can't be that bad because I can load games from an SD2IEC SD drive connected to the serial bus of my MAX10 board !!

I was hoping to be able to provide fixes and improve the compatibility of the core for others, but I'm lacking in VHDL experience and the whole purpose of porting the VIC core to start with was to learn VHDL !!

I appreciate that the VIC core isn't a priority when it comes to FPGA Arcade, but would anyone be interested in me highlighting things that don't work for me and validating if they don't work with the FPGA Arcade version ??  If problems exist on the FPGA Arcade builds of the core as well I'm willing to try to do what I can in order to address the issues and I would welcome being able to talk with others to brainstorm ideas !

Any thoughts appreciated.

Kevin.

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Tue, 11 Apr 2017 14:34:32 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10351#p10351
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10131#p10131 Thanks! Tested that core, did not change anything...

However, don't get distracted too much. There are other cores I'd like to see evolve more urgently wink

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Mon, 13 Mar 2017 18:05:24 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10131#p10131
<![CDATA[Re: VIC20 core talk]]> http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10119#p10119 (I'll change the build script so it's not called loader actually, bit confusing)

In the .ini file for the core,  the "bin = xxx" points at the binary.

info = "---- Joystick in Port A ----"
info = "-Keyboard in lower PS/2 in -"

bin = loader.bin

# sets initial clocking (PLL)
#CLOCK = NTSC
#

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Sun, 12 Mar 2017 21:48:12 +0000 http://www.fpgaarcade.com/punbb/viewtopic.php?pid=10119#p10119