I'll try and give daily updates on the Amiga core.
I have had to back off a little just to get something out - I will continue to tidy it up as we go along.
I've just finished converting the autoconfig PICs to VHDL and added them to the Amiga core - which is now VHDL.
Most of the modules in this are derived from Minimig source by Jakub (Verilog) and customized for the Replay environment - for example sync clocking and other enhancements. The core is mated to the new OSD, system controller and general replay IO. There are a lot of system level changes, for example the ARM now loads up the ROMs directly into DRAM at startup, so lot's of clean up done.
The cache controller has been tidied up but I still have some timing problems.
Running some simulation now to sanity check everything, but I think we are still a few days away.
/Mike