Re: SID talk

hw/replay/cores/lib/sound/m6581

52

Re: SID talk

Ah, thanks!  smile

/WoS

Re: SID talk

I'll try and finish the output stage today so it will make noises.

Re: SID talk

I'm racing Wolfgang here ... check in shortly.

Should be fully operational, although I have some work to do with the log clock dividers in the ADSR envelope generator. The code is all as implemented on the die (hopefully) and I think one of the extracted tables is backwards at the moment.

I've implemented a first cut SVF with hp/bp/lp etc, no idea what it is going to sound like yet wink
/Mike

55 (edited by WoS 2014-03-14 23:25:11)

Re: SID talk

Mike, no worry.
Tomorrow I'll be at a traditional beer festival in Bavaria.
Glasses are 1 L and the beer has 8.2%. And it is required to start next morning with the same again.
So will take a while before I should even consider to do any coding again, so you can easily overtake me cool

/WoS

Re: SID talk

God how I miss the old beer festivals from when I lived in Germany!  German beer and German women.. what a combination!  smile

Re: SID talk

darrin wrote:

German beer and German women.. what a combination!  smile

A recipe for a headache?

Re: SID talk

That sounds like a lot of fun !

Re: SID talk

Just the filter to tweak a little now. ADSR shape looks ok for a first cut wink

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Re: SID talk

Awesome! Hell, how can I learn this stuff?

Re: SID talk

I was a bit unsure of the offset on the analog bits of the SID. I've changed over to signed maths on the multipliers and the ADSR envelope modulates around a 50% value. I think this is how the real SID behaves. Later on I'll make some measurements of a real vs the core to confirm. I'm also not sure how much headroom there is, and if not how the clipping works. For now, the FPGA version has sufficient headroom not to clip - but this may not be the case in the real device.
/MikeJ

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Re: SID talk

Checked in. Filters need some work, but the rest looks ok in the sim, and should be very close to the real chip.
Anybody have measurements from a real chip on the voice dac? I would like to implement a table to approximate the bug/r-2r matching errors in the 6581 dacs.
/MikeJ

63 (edited by WoS 2014-03-17 17:03:21)

Re: SID talk

Back alive. Slowly start typing again... wink

Edit: Johey worked on the keyboard already, so hook in SID and the 1541 and off we go for some pokes to get some sound out if it   cool

/WoS

Re: SID talk

Thought you might like to see my test SID collection wink

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Re: SID talk

MikeJ wrote:

Thought you might like to see my test SID collection wink

It would be interesting so see the backside of the chips... most fakes can easily be spotted!

BTW: I still have a few hundred (no kidding) SIDs! In case you need some test chips?

Here's some work I did in the past reengineering the SID chip:

http://oms.wmhost.com/misc/Wolf_6581_EnvelopeTab.txt
http://oms.wmhost.com/misc/Wolf_r3_envelope.gif
http://oms.wmhost.com/misc/Wolf_r3_waveform.gif

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Re: SID talk

androSID wrote:
MikeJ wrote:

Thought you might like to see my test SID collection wink

It would be interesting so see the backside of the chips... most fakes can easily be spotted!

BTW: I still have a few hundred (no kidding) SIDs! In case you need some test chips?

Here's some work I did in the past reengineering the SID chip:

http://oms.wmhost.com/misc/Wolf_6581_EnvelopeTab.txt
http://oms.wmhost.com/misc/Wolf_r3_envelope.gif
http://oms.wmhost.com/misc/Wolf_r3_waveform.gif

Another file I found in my vault... :-)

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Re: SID talk

androSid - Hello and most welcome.
I collected most of your notes above when I started the design - the tri_ringmod.txt I didn't have, thanks. I've followed some of the layout from the die extraction when there was confusion.

The next step is to mount one of the "real" chips (I do have one known genuine one as well) on my test card and run it in parallel with the RTL. I can read the envelope/osc registers back every cycle and do a hardware compare in the FPGA.

Hopefully this will find any remaining gremlins. I'll get the code up on the public repository when I get a moment. Mail me if you want access to the developer SVN to have a play.

I'll take a piccy of the backside once I move flat next week, they are packed away. They come from my China supplier, but they have a pretty good track record. The original idea was to practice decap with them, but now we are thinking a network analyser between the filter in and out pins may be easier...
Best,
MikeJ

68 (edited by androSID 2014-09-17 19:09:23)

Re: SID talk

MikeJ wrote:

androSid - Hello and most welcome.
Hopefully this will find any remaining gremlins. I'll get the code up on the public repository when I get a moment. Mail me if you want access to the developer SVN to have a play.
I'll take a piccy of the backside once I move flat next week, they are packed away. They come from my China supplier, but they have a pretty good track record. The original idea was to practice decap with them, but now we are thinking a network analyser between the filter in and out pins may be easier...
Best,
MikeJ

I'd really take a look at the repository - though my knowledge of VHDL is quite limited. (I'm more into C/C++) :-)
In case you need more 100% genuine chips just let me know... I'll happily donate some (R2, R3 or R4/R4AR) if it helps.

I did the annotation on the SID die reconstruction mostly in 2010/11 when I was commuting a lot; so my
memories need some kind of refresh now. What I remember is that there's still one unsolved mystery:

The one clock delay between 6581 and 8580R5 (at least when reading the noise generator).

Re: SID talk

Interesting. I'll see if I can reproduce that. I sent you an email.

70 (edited by androSID 2014-09-18 07:57:55)

Re: SID talk

Here I found a small documentation of the "full binary adder" logic used
on the oscillator section of the SID.

The file represents the circuit used for data bit 0 (D0) of the OSC and
is exists 12 times in each OSC section.


$02/$03 - chip select
D0 - input D0
RST - reset signal

ps: Having tested/listened to hundreds of SIDs I can state that the sound
charateristic of a SID chip is completely independent from it's revision
and also doesn't depend on the batch it was produced.
IOW: Two chips from the same time and batch almost always sound
differently.
However: Chips from R2 (and maybe R3) tend to have a weaker filter or "lighter sound".
And the darkest sound always came from R4 or R4AR chips.

R5 (8580R5) chips sound almost identical. Hard to hear differences between chips - no
matter when they were produced.

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71 (edited by androSID 2014-09-18 08:31:04)

Re: SID talk

wolfgang wrote:

Here it is even simpler, it is only required to check the assumed 23bit polynomial (x^22+x^17+1) against the output pattern (but only if I find this program again I set up that day...).

The "assumed" polynomial is correct. I checked that long time ago when working on the SID reconstruction.

Please see:

http://oms.wmhost.com/misc/Wolf_r3_waveform.gif

Here you can see the two XORs that are fed back to the input of the LFSR circuitry.
The signals they use are from bit 17 and 22 of the LFSR.

Re: SID talk

Thanks for the feedback. I'm looking forward to running these up soon. I'll check in the test harness as well and log any differences in the digital section. We should be able to get the digital part cycle and bit accurate quite quickly.

For the analogue section, I would first like to model the known non-linearities in each DAC with a 1d LUT.
Then it's really a case of how much DSP we want to thrown at the filters models...

73 (edited by androSID 2014-09-18 10:33:29)

Re: SID talk

MikeJ wrote:

Thanks for the feedback. I'm looking forward to running these up soon. I'll check in the test harness as well and log any differences in the digital section. We should be able to get the digital part cycle and bit accurate quite quickly.

For the analogue section, I would first like to model the known non-linearities in each DAC with a 1d LUT.
Then it's really a case of how much DSP we want to thrown at the filters models...

I think that the non-linearity of the DAC should be easier to implement than the filter section.
IIRC the saturation of the nonlinear FETs were one of the main causes for the filter behavior as
the filter parameters changed with the output voltage of the DAC driving the FETs into saturation effects.

Re: SID talk

Welcome androSID! I bought eight perfectly working 8580 chips from you a few years ago, for the MB6582 box. Happy you found your way to the Replay side. big_smile

Re: SID talk

androSID and I have been having a good chat on email, which has already led to a few layout related improvements to the code ...