Topic: Simulation lib and DRAM size
While I remember ....
there is a setting "part_mem_bits" which tells the DRAM model how much memory to use.
I've set it to 24, so the whole address space of the standard machine is in the simulator. Probably slows it down a little.
is a DRAM emulator for use with the CPU testbench. It implements in VHDL a memory where blocks are created on demand
if mem_storage(row) = null then
mem_storage(row) := new mem_block; --dynamically create some more ram
for i in 0 to 63 loop
mem_storage(row)(i) := (others => 'X');
What I should probably do, is put a switch in the generic testbench which bypasses the Replay memory controller and simple verilog RAM module. This would speed up most test benches hugely.
We could also then direct load bin or hex files to the memory rather than getting Replay hardware to load over emulated SPI.