1 (edited by hicks 2017-06-25 11:10:09)

Topic: Clock choice

I'm looking into doing an Acorn Electron core and need a 16MHz clock for the ULA. My question is how to best generate that via the replay.ini?

A clk_a at ~256MHz would give an ena_sys of 16MHz, but the datasheet for the PLL says the max output freq is 167MHz. Whilst a clk_a of ~64MHz gives a sys_clk of 16MHz which I could use raw into the ULA rather than gated with ena_sys. But I recall something about clk_a also being used for SPI and needing to be reasonably high? Is 64MHz too low?

The option I'm leaning towards atm is clk_a of ~128MHz to give a sys of 32MHz then the core would ignore sys_ena and instead use a 1 in 2 ula_ena.

Deriving a new 1 in 2 "ula_ena" clock from sys_clk isn't an issue, but are there implications for using that in the core in place of ena_sys? I imagine anything running in the replay lib and exposed to the core (that uses sys_clk) will be based on 1 in 4 sys_ena, so there'd be a timing mismatch to deal with. DDR for example would need to have two ula_ena clocks before the read is ready.

Are there any better ways to handle this?

Re: Clock choice

*(Update on the above). I solved this by making a new clock enable, where the ula clocked twice as quick as the system enable.
It meant doing the DDR reads, and needed a bit more care to always do the setup on the correct clock, but it seemed to work.