Replay2 update

It’s been an exciting two months learning about the new Intel Agilex5 and the RK3588 used in our new Replay2 platform. The design and schematic are nearly completed – after a number of last minute changes/improvements.

Samples of the part are on the way and we’ll post some detailed layout images and specs of the board in the near future.

I’m also setting up a new X account, and then this website will get updated and new forums added.


The Agilex5 is a bleeding edge new FPGA which is faster and larger than any other competing Retro gaming system. The part we are using has dual 64 bit A55 and dual 64bit A75 processors on board. It’s the natural successor to the CycloneV device used on the MISTer DE10-nano board.


Replay2 will be open source, we’ve started to move the repositories onto github. There is a lot of work to do, and it’s hugely delayed, but I think it’s been worth all the changes and it’s going to be an incredible platform.



Replay2 Teaser

It’s been a long time coming, but we are really excited to announce that Replay2 will be based around the Intel Agilex5 FPGA.


Replay2… the saga continues

It’s been a long time coming, but the desk is clean and ready for the first hardware prototype, hopefully December ’23…….

Good things come to those who wait.



Namco CUS34 – second mode.

I’m fully focused on Replay2 currently, but just a quick update on the Namco CUS34 replacement. I really wanted to complete the alternative mode used on ToyPop and Libble Rabble.

Using my 20 year old bit of vero-board, I can compare the replacement and real chip directly. The logic analyzer connects to both parts and dip switches let me isolate outputs from the replacement while still feeding it all the inputs. I worked out which pins where inputs/outputs and bidirectional first by isolating each pin and applying pull ups/downs.

I’ve got it all running now, and the advantage of this direct compare is that the analyzer can tell me if there are any differences at all between the chips, but also I can compare and tweak the timing. The CPLD used is way faster than the original and sometimes delay cells need to be used to add some hold timing. The disadvantage compared to reverse engineering the die is that I can only test functionality used in the game.

Now I understand what the chip does, I can put it back on the Zynq tester shown in the previous post and apply some unusual signals just to make sure it works correctly.

I’ve seen posts from a Japanese chap who has reverse engineered the die. Great job, but no source code as far as I can see yet.The code for this, along with all the other reverse engineer chips will be in the public R2 git repository, and used in our latest FPGA cores.

I’ve been shipping replacement modules for many years for the Namco28 pin chips (and other parts) so message me if you are in need. I have quite a few in stock currently.