Gearing up for Replay2 Production

Replay2 is still in layout and a few things are awaiting design closure (primarily memory configuration). The FPGA chosen is a Xilinx Ultrascale+ device (super fast) with Quad core A-53s, dual R5s and a Maii GPU.

The CPU section has DDR4 DRAM, and the FPGA most likely 2 x DDR3 memories. The board has a display port output for the CPU side, DVI/HDMI as well as a high quality DAC for analog output and the JAMMA adapter.

I hope to get some more details posted soon. I’ve started to order parts for the prototype and this morning visited a local SMD prototyping house to see if they could build it.

The production boards will most likely be massed produced by a well known hobby hardware manufacturer, but it’s handy to get a few boards quickly done for initial debug (and smoke test).

MikeJ

 

 

68060 Ethernet and SD card support

Our resident coding genius Erique has been hard at work finishing off driver support for the DB. Source and the ROM binary can be round here : https://github.com/FPGAArcade/amiga_code

Please also take a look at the FAQ here:

How to install and setup the 060 Daughterboard Amiga

 

The Ethernet (unlike some other solutions) relies on a 16 bit parallel interface MAC which sits on the ‘060 local bus. There is scope for improving performance, but first I want to increase the CPU frequency as high as possible. Many rev6 060s will work at 113MHz.There is a jumper on board to increase the core voltage by ~5% if necessary via the dedicated DC/DC driving the CPU.

Another question I’ve been asked…  We have 128MB of directly connected SDRAM, why not use DDR2/3, surely that’s “faster”. No. The SDRAM can burst read/write 4 words at the maximum speed the CPU can, so there is no performance gain by using a higher frequency (unless you want to share the memory with another controller – but we have the main board DDR memory for that). The real killer is read latency. If we put an FPGA bridge in the path, the reads would have to pass through the FPGA controller to the memory and back again. Admittedly the 060 on die cache solves this problem for many cases, but not all.  For R2 we will have very high speed memories on the main board, but I think I will still add an option for local SDRAM for this reason.

The picture below shows Erique’s homebrew SD card adapter. This allows him to connect a logic analyzer while connected to the SD card …. and the board being in it’s case. Neat!

Github release repository and Crystal Castles core!

Still a lot of work going on to move the codebase to the new github repositories and roll out multiplatform support – initially for the Arduino Vidor.

Some binaries have been put here while we faff about

https://github.com/FPGAArcade/replay_release

 

Including Crystal Castles by the fabulous Chris B.

68060 Daughterboard rear I/O shield arrives

While there is a lot of exciting new stuff going on, I’m still trying to finish off some old commitments.

Thanks to some CAD help from the team and the fantastic guys in Taiwan we have received the laser cut ATX I/O panels.

Contact me if you want one. It only fits on B2 boards (not 1.0B) without modification. If you have a previous I/O shield, this one will also fit.

(Note in the picture below I’ve not got the board screwed together so the holes are not quite aligned)