Still working on reformatting the archive, hopefully Christian well get some time to tidy up the PDFs.
Here’s the unsorted ones I extracted. I’ve contacted the original tool vendor, just in case they will help us with the recovery process.
Well, summer is now over and it’s time to crack on with the FPGA work. I’m still busy repairing the last few boards, and work is well under way on the daughterboard and new production run.
I’ve been chatting with a couple of guys over on atari-forum regarding the Atari ST ASICs.
http://www.chzsoft.de/asic-web/ has been able to print out some of the ASIC drawings found in an Atari archive. I’m working with him to see what’s useful, and contributing my work back. I’ll stick it all in the public SVN asap.Finally, here’s a super die scan of the MMU C0205912-38 by Ijor./Mike
I’m starting the work on updating the website and servers. The developers SVN will be off line for a few moments today.
You may have noticed the forum is down. This appears to be a problem with the hosting company after an update.
I have run a full back now and we are working on it ….
And it’s all ok again.
The forum is really the place to see regular updates, but I thought it was time for a summary here.
The Amiga code is pretty stable. Work is being done to add RTG interlaced modes and increase CPU performance further, but the main focus at the moment is on hardware.
I’ve been working with some new suppliers and assemblers, using my Namco 28 pin ASIC replacement as a test. They have just arrived back and look very nice :
I need to test these, then I’ll update (ok, write) this part of the website. These modules are used to replace a number of Namco devices in old arcade games.
In other news, the 68060 daughterboard can now be completed. The main problem was a lack of the connectors in small volume – MOQ was 500.
I’ve managed thanks to Samtec to get a smaller amount, so I can get on and produce the board.
I’ve released a new version of the Amiga core (svn.fpgaarcade.com).
New features :
48M XRAM mapped as Chip and all chipset DMA pointers support 64M addressing (optionally enabled in OSD / .ini file)
CPU cache stable – 2 way I + D with full snoop. ~16000 AIBB Dhrystones
Filtered & Mono audio
RTG over analog/DVI/HDMI with hardware sprites and dedicated blitter engine. 1024×768 at 16 bit, 1280×1024 at 8 bit.
(1920x1080i works over analog but not digital for some reason at the moment)
Real Amiga keyboard support (thanks to Erique)
I’m going to spend some time now updating the website and working on the AGA debug hardware so we can further improve compatibility. I also have some CPU upgrades in the pipeline which will allow x2-x3 speed up hopefully.
A lot of work has been done both on the CPU to increase compatibility, and the core to get the cache working and timing closure.
The design is completely constrained and this results in a very stable platform
2K Instruction plus 2K Data cache with full chipset snoop on both.Performance is around 11.3 mips / 10800 dhrystones with sysinfo 4.0.
The RTG dedicated blitter is working, and this coupled with the fast hard disk speed makes the system feel highly responsive.
I’ve added some modes to the scan doubler to help DVI monitors work.
Low pass filters on the audio (optional).
HRTMon cart working again with custom & cia shadow and full VBR support. Config is editable from the .INI file.
More details on the forum.
The latest Amiga AGA core is in beta with support for P96 compatible RTG. It also includes a hardware blitter engine which is used by the card driver to speed up window movements.
There is still work to do increasing the pixel clock, but it’s nice to see these modes working cleanly over DVI/HDMI. Thanks especially to Jim Drew for work on the driver.
See the forum for more details.
Time for another update. Sometimes it seems things go a bit quiet here – while it’s true September is a busy month with my other (money earning) activities, there has been a lot going on with Replay.
I’ve just finished the tweaks for the DDR controller needed for the vector games (Asteroids and StarWars) and the RTG graphics mode for the Amiga.
Now we can get 2 x 128bits per system clock (~8MHz) from the memory system, which is enough to run the CPU at full speed and decent resolution on the RTG. The RTG is fully written, including the driver, but there is still some work to do debugging the new code.
I’ve completed the Amiga cache system as well, but it requires some tuning to get timing closure still. This gives about x4 performance increase on the current core. The cache features prefetch which will read ahead of the CPU and try to keep the buffer as full as possible. For burst access, the memory system can keep up with the CPU, but I noticed today that it’s possible for DRAM refresh to get locked out. I’m adding a mode (refresh panic) which asks the cache to hold off for a cycle while the DRAM catches up with the house keeping.
I’m still working hard to test and ship boards, and I’m heading to China shortly to see how the production run is going.