Konami 40 pin IC replacement

Finally, after being stuck in Swedish customs for nearly a month (thanks PostNord), the PCB for my 40 pin Konami 503 ASIC replacement has arrived. I’m experimenting with an Atmel 5V CPLD on these, rather than the old Altera MAX7064 which is getting hard to get,...
Last Replay1 shipped….

Last Replay1 shipped….

The final complete R1 & 68060 DB to ship Well, actually the last (I thought) Replay1 shipped years ago, but I’ve had one sitting around which failed production test. When a core boots up, the ini file for that core tells the software which files to upload...
Gyruss reverse engineering

Gyruss reverse engineering

Here at FPGAArcade we’ve always tried to reproduce retro hardware for preservation as accurately as possible. When I did the first Pacman design years ago it was quite easy as there were only a few custom ICs. I built some analysis hardware you can find way back...
Replay2 proto-board arrived

Replay2 proto-board arrived

We’ve bought a number of Ultra96 boards which contain a similar FPGA to the target device on Replay2. This will kick start development, especially on the Linux side. I’m also designing a small add-on board with the video output devices we’ll use on...

Replay2 first mock up

Very rough CAD drawing to play with IO connectors Replay2 is now in PCB design. We are using a Xilinx Ultrascale+ MPSoC device which combines a fast FPGA and a 64 bit Cortex A53 cluster. The device is built on 16nm FinFET+ logic. The processor system runs up to...

Replay2 …. the saga continues

So first, I must apologise for it being quiet here news-wise. The active development is mostly on Slack now, but I will try and post updates here more often. So, Replay2 stalled. The issue was the excellent price/performance of the DE10 board (used in the Mister...
Replay2

Replay2

Over the years there has been a lot of frustration about the lack of Replay boards. The main issue was the lack of quality control on components from China which caused a lot of rework effort. In retrospect, we should probably have thrown these away and built new...
ALICE decap and imaged

ALICE decap and imaged

We commissioned the decap and scanning of Alice, probably the most important custom chip in the Amiga. Thanks to John Hertell for the device, and to John McMaster for the decap and scan. Here is the image data in full :...
Replay 68060 daughterboard

Replay 68060 daughterboard

The layout for the Replay 68060 board is complete and has been sent for manufacture. It adds 128MB of local RAM, USB, Ethernet, RTC as well as additional Midi and LED IO connectors. The picture below is a quick mock-up to see if the components actually fit 🙂  ...
More recovered Atari documents

More recovered Atari documents

Still working on reformatting the archive, hopefully Christian well get some time to tidy up the PDFs. Here’s the unsorted ones I extracted. I’ve contacted the original tool vendor, just in case they will help us with the recovery process.  ...
Back to school, and Atari die shots….

Back to school, and Atari die shots….

Well, summer is now over and it’s time to crack on with the FPGA work. I’m still busy repairing the last few boards, and work is well under way on the daughterboard and new production run. I’ve been chatting with a couple of guys over on atari-forum...
Server update

Server update

I’m starting the work on updating the website and servers. The developers SVN will be off line for a few moments today. /Mike

Forum down (Now fixed)

You may have noticed the forum is down. This appears to be a problem with the hosting company after an update. I have run a full back now and we are working on it …. … And it’s all ok again. Happy Friday!

Hardware stuff

The forum is really the place to see regular updates, but I thought it was time for a summary here. The Amiga code is pretty stable. Work is being done to add RTG interlaced modes and increase CPU performance further, but the main focus at the moment is on hardware....
Amiga AGA core stable release

Amiga AGA core stable release

I’ve released a new version of the Amiga core (svn.fpgaarcade.com). New features : 48M XRAM mapped as Chip and all chipset DMA pointers support 64M addressing (optionally enabled in OSD / .ini file) CPU cache stable – 2 way I + D with full snoop. ~16000...
Cache and RTG operational in Amiga core

Cache and RTG operational in Amiga core

A lot of work has been done both on the CPU to increase compatibility, and the core to get the cache working and timing closure. The design is completely constrained and this results in a very stable platform Latest features: 2K Instruction plus 2K Data cache with...

More boards on final test

Taking a quick break from the Amiga core development to ship some hardware. Workbench is full, this is the overflow storage! (These are all going to the distributors. If you were on the original list please email me. I also have boards at reduced cost for developers...

Amiga RTG (Graphics card) working and in Beta

The latest Amiga AGA core is in beta with support for P96 compatible RTG. It also includes a hardware blitter engine which is used by the card driver to speed up window movements.   There is still work to do increasing the pixel clock, but it’s nice to see...

Amiga roadmap and DDR memory fun

Time for another update. Sometimes it seems things go a bit quiet here – while it’s true September is a busy month with my other (money earning) activities, there has been a lot going on with Replay. I’ve just finished the tweaks for the DDR...
Amiga core update – Blitter issues and chipset timing

Amiga core update – Blitter issues and chipset timing

The AGA core is pretty stable now, but one issue which has been haunting me for ages is some blitter operations go wrong and leave garbage on the screen. I’ve been working with Jim Drew, who pointed me at some source code released by DMA designs for Menace...